Memory can generally be characterized as either volatile or non-volatile. Volatile memory, for example, random access memory (RAM), requires constant power to maintain stored information. Non-volatile memory does not require power to maintain stored information. Various non-volatile memories include read only memories (ROMs), erasable programmable read only memories (EPROMs), and electrically erasable programmable read only memories (EEPROMs).
A one-time programmable memory device is a type of ROM that may be programmed one time and may not be reprogrammed. Some one time programmable memory devices use an anti-fuse as the programmable element. An anti-fuse may exist in one of two states. In its initial state, (“un-programmed”) the anti-fuse functions as an open circuit, preventing conduction of current through the anti-fuse. Upon application of a high voltage or current, the anti-fuse is converted to a second state (“programmed”) in which the anti-fuse functions as a line of connection permitting conduction of a current. During a readout of the device, an un-programmed anti-fuse corresponds to a logic value, for example “0”, and a programmed anti-fuse represents another logic value, for example “1”.
An anti-fuse may be implemented using a capacitor or a MOSFET. When programming an anti-fuse MOSFET, the process begins with application of voltage stress to the MOSFET gate, which causes defects to appear in the gate-oxide. As the defect density increases, eventually a critical level is reached where a current may flow through the oxide through a chain of defects. The thermal effects of the current solidifies this newly formed conductive channel, or “pinhole,” through the oxide. For a capacitor anti-fuse, a programming voltage causes a breakdown in the capacitor dielectric and a resulting short across the capacitor electrodes in a similar manner as described above.
FIG. 1 shows a schematic of one proposal for anti-fuse cells arranged in an array 10 of a one-time programmable memory device 10. Each cell 20 contains an anti-fuse element 30, common gate transistor 40 connected to one node of anti-fuse element 30, and switch transistor 50 having a gate connected to a word line WL1 and one source/drain terminal connected to a bit line BL1 and another connected to transistor 40. A second node of the anti-fuse element 30 is connected to a programming voltage source line VCMN.
During the readout, the anti-fuse element 30 is directly driving the entire column output line, shown as bit line BL1, which has a high load. In order to meet typical programming and readout speed requirements, a low resistance anti-fuse is required to drive the high column load, which in turn requires a large common gate transistor 40 and switch transistor 50 to deliver the current necessary to lower the resistance of the anti-fuse.
A method, apparatus and system providing an improved anti-fuse cell and array structure are desired which provide a smaller anti-fuse area, increased readout speed, and lower power requirements.